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<html xmlns="http://www.w3.org/1999/xhtml"><head><link rel="stylesheet" type="text/css" href="insn.css"/><meta name="generator" content="iform.xsl"/><title>ADDHA</title></head><body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h2 class="instruction-section">ADDHA</h2><p>Add horizontally vector elements to ZA tile</p>
      <p class="aml">Add each element of the source vector to the corresponding active element of each horizontal slice of a ZA tile. The tile elements are predicated by a pair of governing predicates. An element of a horizontal slice is considered active if its corresponding element in the second governing predicate is TRUE and the element corresponding to its horizontal slice number in the first governing predicate is TRUE. Inactive elements in the destination tile remain unmodified.</p>
      <p class="aml">ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</p>
    
    <p class="desc">
      It has encodings from 2 classes:
      <a href="#iclass_per_word">32-bit</a>
       and 
      <a href="#iclass_per_doubleword">64-bit</a>
    </p>
    <h3 class="classheading"><a id="iclass_per_word"/>32-bit<span style="font-size:smaller;"><br/>(FEAT_SME)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">0</td><td class="l">0</td><td class="r">1</td><td class="l">0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td colspan="3" class="lr">Pm</td><td colspan="3" class="lr">Pn</td><td colspan="5" class="lr">Zn</td><td class="lr">0</td><td class="lr">0</td><td class="lr">0</td><td colspan="2" class="lr">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="7"/><td/><td colspan="2"/><td colspan="3"/><td class="droppedname">V</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td/><td/><td colspan="2"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addha_za_pp_z_32"/><p class="asm-code">ADDHA   <a href="#sa_zada" title="ZA tile ZA0-ZA3 (field &quot;ZAda&quot;)">&lt;ZAda&gt;</a>.S, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field &quot;Pn&quot;)">&lt;Pn&gt;</a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field &quot;Pm&quot;)">&lt;Pm&gt;</a>/M, <a href="#sa_zn" title="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a>.S</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSME.0" title="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
constant integer esize = 32;
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</p>
    <h3 class="classheading"><a id="iclass_per_doubleword"/>64-bit<span style="font-size:smaller;"><br/>(FEAT_SME_I16I64)
          </span></h3><div class="regdiagram-32"><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="l">1</td><td class="r">1</td><td class="l">0</td><td>0</td><td>0</td><td>0</td><td>0</td><td>0</td><td class="r">1</td><td class="lr">1</td><td class="l">0</td><td>1</td><td>0</td><td>0</td><td class="r">0</td><td class="lr">0</td><td colspan="3" class="lr">Pm</td><td colspan="3" class="lr">Pn</td><td colspan="5" class="lr">Zn</td><td class="lr">0</td><td class="lr">0</td><td colspan="3" class="lr">ZAda</td></tr><tr class="secondrow"><td colspan="2"/><td colspan="7"/><td/><td colspan="5"/><td class="droppedname">V</td><td colspan="3"/><td colspan="3"/><td colspan="5"/><td/><td/><td colspan="3"/></tr></tbody></table></div><div class="encoding"><h4 class="encoding"/><a id="addha_za_pp_z_64"/><p class="asm-code">ADDHA   <a href="#sa_zada_1" title="ZA tile ZA0-ZA7 (field &quot;ZAda&quot;)">&lt;ZAda&gt;</a>.D, <a href="#sa_pn" title="First governing scalable predicate register P0-P7 (field &quot;Pn&quot;)">&lt;Pn&gt;</a>/M, <a href="#sa_pm" title="Second governing scalable predicate register P0-P7 (field &quot;Pm&quot;)">&lt;Pm&gt;</a>/M, <a href="#sa_zn" title="Source scalable vector register (field &quot;Zn&quot;)">&lt;Zn&gt;</a>.D</p></div><p class="pseudocode">if !<a href="shared_pseudocode.html#impl-aarch64.HaveSMEI16I64.0" title="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
constant integer esize = 64;
integer a = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pn);
integer b = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Pm);
integer n = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(Zn);
integer da = <a href="shared_pseudocode.html#impl-shared.UInt.1" title="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</p>
  <div class="encoding-notes"/><h3 class="explanations">Assembler Symbols</h3><div class="explanations"><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;ZAda&gt;</td><td><a id="sa_zada"/>
        
          
        
        
          <p class="aml">For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.</p>
        
      </td></tr><tr><td/><td><a id="sa_zada_1"/>
        
          
        
        
          <p class="aml">For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Pn&gt;</td><td><a id="sa_pn"/>
        
          <p class="aml">Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Pm&gt;</td><td><a id="sa_pm"/>
        
          <p class="aml">Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.</p>
        
      </td></tr></table><table><col class="asyn-l"/><col class="asyn-r"/><tr><td>&lt;Zn&gt;</td><td><a id="sa_zn"/>
        
          <p class="aml">Is the name of the source scalable vector register, encoded in the "Zn" field.</p>
        
      </td></tr></table></div><div class="syntax-notes"/>
    <div class="ps"><a id="execute"/><h3 class="pseudocode">Operation</h3>
      <p class="pseudocode"><a href="shared_pseudocode.html#impl-aarch64.CheckStreamingSVEAndZAEnabled.0" title="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
constant integer VL = <a href="shared_pseudocode.html#impl-aarch64.CurrentVL.read.none" title="accessor: integer CurrentVL">CurrentVL</a>;
constant integer PL = VL DIV 8;
constant integer dim = VL DIV esize;
bits(PL) mask1 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[a, PL];
bits(PL) mask2 = <a href="shared_pseudocode.html#impl-aarch64.P.read.2" title="accessor: bits(width) P[integer n, integer width]">P</a>[b, PL];
bits(VL) operand_src = <a href="shared_pseudocode.html#impl-aarch64.Z.read.2" title="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
bits(dim*dim*esize) operand_acc = <a href="shared_pseudocode.html#impl-aarch64.ZAtile.read.3" title="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</a>[da, esize, dim*dim*esize];
bits(dim*dim*esize) result;

for col = 0 to dim-1
    bits(esize) element = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_src, col, esize];
    for row = 0 to dim-1
        bits(esize) res = <a href="shared_pseudocode.html#impl-shared.Elem.read.3" title="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_acc, row*dim+col, esize];
        if (<a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask1, row, esize) &amp;&amp;
              <a href="shared_pseudocode.html#impl-aarch64.ActivePredicateElement.3" title="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask2, col, esize)) then
            res = res + element;
        <a href="shared_pseudocode.html#impl-shared.Elem.write.3" title="accessor: Elem[bits(N) &amp;vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim+col, esize] = res;

<a href="shared_pseudocode.html#impl-aarch64.ZAtile.write.3" title="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</a>[da, esize, dim*dim*esize] = result;</p>
    </div>
  <h3>Operational information</h3><p class="aml">If PSTATE.DIT is 1:</p><ul><li>The execution time of this instruction is independent of:
              <ul><li>
                  The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.
                </li><li>The values of the NZCV flags.</li></ul></li><li>The response of this instruction to asynchronous exceptions does not vary based on:
              <ul><li>
                  The values of the data supplied in any of its operand registers when its governing predicate registers contain the same value for each execution.
                </li><li>The values of the NZCV flags.</li></ul></li></ul><hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="index.html">Base Instructions</a></div></td><td><div class="topbar"><a href="fpsimdindex.html">SIMD&amp;FP Instructions</a></div></td><td><div class="topbar"><a href="sveindex.html">SVE Instructions</a></div></td><td><div class="topbar"><a href="mortlachindex.html">SME Instructions</a></div></td><td><div class="topbar"><a href="encodingindex.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="shared_pseudocode.html">Shared Pseudocode</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">
      Internal version only: isa v33.62, AdvSIMD v29.12, pseudocode v2023-03_rel, sve v2023-03_rc3b
      ; Build timestamp: 2023-03-31T11:36
    </p><p class="copyconf">
      Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved.
      This document is Non-Confidential.
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